1. Technical Field
The present invention generally relates to semiconductor devices and methods of fabricating semiconductor devices, more particularly, to methods of reducing merging of semiconductor epitaxial growth on adjacent fins of a FinFET.
2. Background Information
Three-dimensional field-effect transistors (FinFETs) are currently being developed to replace conventional planar metal oxide semiconductor field-effect transistors (MOSFETs) in advanced complementary metal oxide semiconductor (CMOS) technology due to their improved short-channel effect immunity and higher on-current to off-current ratio (Ion/Ioff). As is known, the term “fin” refers to a vertical structure within or upon which are formed, for instance, one or more transistors or other semiconductor devices, such as passive devices, including capacitors, diodes, etc. As the density of semiconductor integrated circuits increases and the corresponding size of circuit elements decreases, significant challenges may arise, due to issues related to, for instance, merging of semiconductor epitaxial growth on adjacent fins of a FinFET, resulting in challenges such as, for instance, contact spiking.
Accordingly, a need exists to reduce merging of semiconductor epitaxial growth on adjacent fins of a FinFET.